Sutradhar

Open Formal EDA & Chiplet Assembly Flow

Thesis

Control over compute composition via chiplet assembly and formal verification is essential for technological sovereignty. We must master the art of integrating open chiplets over mature nodes with guaranteed correctness.

What it is

A comprehensive open toolchain featuring:

RTL → package flow with embedded formal proofs
Die-to-die interface contracts and verification
Thermal and timing analysis frameworks
Package-level verification suite

Why it matters

Breaking the soft embargo of EDA tooling is crucial for India's semiconductor ambitions. By making the assembly recipe a national asset, we create a path to sovereign system integration capabilities.

This enables India to leverage mature nodes while maintaining control over critical system composition and verification.

Demonstration Path

v0.1 - Basic Integration Flow

2-chiplet composition with validated models
Thermal and timing verification
Basic interface contract checking

v0.2 - Advanced Features

Automated scan chain insertion
Built-in self-test generation
Enhanced package-level verification

Contribute

Join us in building India's chiplet integration capabilities:

Chiplet Integration Test Generation